Access internal module signals via bind if internal signals depends on generate block

SystemVerilog
, , ,
1

Hey,

Lets say I have the following :


// Original module
module dut #(parameter WIDTH = 5, parameter EN_FEAT = 1) ();
    wire  [WIDTH-1:0] dut_internal_bus;
    generate
        if (EN_FEAT) begin : g_EN_FEAT
            wire feat_wire = |dut_bus;
        end
    endgenerate
endmodule

// Module for binding
module bdut #(parameter WIDTH = 5, parameter EN_FEAT = 1) (
    input [WIDTH-1:0] dut_internal_bus,
    input feat_wire);
endmodule

module top();
   dut#() dut1();

   initial begin
      #2;
      $finish();
   end
endmodule

Now, for the bind itself, if I only wanted to connect internal signals (in a scenario I don’t have the feat_wire in the bdut) i would just a wildcard :


// The binding..
bind dut bdut#(
    .WIDTH(WIDTH),
    .EN_FEAT(EN_FEAT)
) a_inst(
    .*
    );

If I want the internal signal, I would have to do something like this I guess ( or not? because i remember using wildcard and named connections is not allowed to be mixed…)


// The binding..
bind dut bdut#(
    .WIDTH(WIDTH),
    .EN_FEAT(EN_FEAT)
) a_inst(
    .*,
    .feat_wire(g_EN_FEAT.feat_wire)
    );

Is there any way to dodge this issue and based on the EN_FEAT to do the connections? Must I create 2 different modules and bind by instance ? (lets say i have 100 DUT modules in the system, half with EN_FEAT=1 and half with EN_FEAT=0)

Thanks.