Topics tagged macros

Topic	Replies	Views	Activity
Can I have one macro which adds code in 3 different location? SystemVerilog SystemVerilog , macros , covergroup	1	144	September 23, 2023
Define from one package are visible in another package SystemVerilog SystemVerilog , Package , macros , system-verilog-package-compilation	7	7060	April 20, 2022
Use of if/else conditions around assign statements in Macros SystemVerilog SystemVerilog , macros	3	2582	August 25, 2021
Using Macros to create Covergroups SystemVerilog SystemVerilog , Coverage , macros	1	760	March 10, 2021
Basic of `define Macros SystemVerilog SystemVerilog , macros , define	2	935	March 17, 2020
Using uvm_component to create sequences UVM UVM , sequence , macros , uvm_component	4	1460	January 20, 2020
Variable in Hierarchical access SystemVerilog SystemVerilog , hierarchy , macros , DUT-parameters	2	1975	September 13, 2019
Problem while using `ifdef..`elsif..`else SystemVerilog SystemVerilog , macros	2	3096	September 7, 2019
Extracting type of variable within a macro SystemVerilog SystemVerilog , macros , typename	4	5633	February 13, 2017
Questa unexpected internal error: vgencode.c(207), verror (vopt-2064) SystemVerilog SystemVerilog , UVM , macros , UVM-Questa , vopt , Questa-102c	1	6410	November 17, 2014
Combination of generate and macro SystemVerilog SystemVerilog , generate , macros	3	7147	August 21, 2014
Macros SystemVerilog SystemVerilog , macros	4	2706	April 25, 2014