Topics tagged macros

Topic	Replies	Views	Activity
Hierarchical path using array SystemVerilog SystemVerilog , macros , define	5	131	October 4, 2024
Regarding Macro substitution SystemVerilog SystemVerilog , macros , macro-substitution	1	171	May 28, 2024
Can I have one macro which adds code in 3 different location? SystemVerilog SystemVerilog , macros , covergroup	1	258	September 23, 2023
Define from one package are visible in another package SystemVerilog SystemVerilog , Package , macros , system-verilog-package-compilation	7	7518	April 20, 2022
Use of if/else conditions around assign statements in Macros SystemVerilog SystemVerilog , macros	3	2928	August 25, 2021
Using Macros to create Covergroups SystemVerilog SystemVerilog , Coverage , macros	1	975	March 10, 2021
Basic of `define Macros SystemVerilog SystemVerilog , macros , define	2	1126	March 17, 2020
Using uvm_component to create sequences UVM UVM , sequence , macros , uvm_component	4	1653	January 20, 2020
Variable in Hierarchical access SystemVerilog SystemVerilog , hierarchy , macros , DUT-parameters	2	2306	September 13, 2019
Problem while using `ifdef..`elsif..`else SystemVerilog SystemVerilog , macros	2	3685	September 7, 2019
Extracting type of variable within a macro SystemVerilog SystemVerilog , macros , typename	4	6027	February 13, 2017
Questa unexpected internal error: vgencode.c(207), verror (vopt-2064) SystemVerilog SystemVerilog , UVM , macros , UVM-Questa , vopt , Questa-102c	1	6774	November 17, 2014
Combination of generate and macro SystemVerilog SystemVerilog , generate , macros	3	7584	August 21, 2014
Macros SystemVerilog SystemVerilog , macros	4	2908	April 25, 2014

Hierarchical path using array

SystemVerilog

SystemVerilog , macros , define

5

131

October 4, 2024

Regarding Macro substitution

SystemVerilog

SystemVerilog , macros , macro-substitution

1

171

May 28, 2024

Can I have one macro which adds code in 3 different location?

SystemVerilog

SystemVerilog , macros , covergroup

1

258

September 23, 2023

Define from one package are visible in another package

SystemVerilog

SystemVerilog , Package , macros , system-verilog-package-compilation

7

7518

April 20, 2022

Use of if/else conditions around assign statements in Macros

SystemVerilog

SystemVerilog , macros

3

2928

August 25, 2021

Using Macros to create Covergroups

SystemVerilog

SystemVerilog , Coverage , macros

1

975

March 10, 2021

Basic of `define Macros

SystemVerilog

SystemVerilog , macros , define

2

1126

March 17, 2020

Using uvm_component to create sequences

UVM

UVM , sequence , macros , uvm_component

4

1653

January 20, 2020

Variable in Hierarchical access

SystemVerilog

SystemVerilog , hierarchy , macros , DUT-parameters

2

2306

September 13, 2019

Problem while using `ifdef..`elsif..`else

SystemVerilog

SystemVerilog , macros

2

3685

September 7, 2019

Extracting type of variable within a macro

SystemVerilog

SystemVerilog , macros , typename

4

6027

February 13, 2017

Questa unexpected internal error: vgencode.c(207), verror (vopt-2064)

SystemVerilog

SystemVerilog , UVM , macros , UVM-Questa , vopt , Questa-102c

1

6774

November 17, 2014

Combination of generate and macro

SystemVerilog

SystemVerilog , generate , macros

3

7584

August 21, 2014

Macros

SystemVerilog

SystemVerilog , macros

4

2908

April 25, 2014