Combination of generate and macro

SystemVerilog
, ,
1

Hi.
I defined the next macro:

`define CONNECT(ARRAY_NAME, CH)\
   assign ARRAY_NAME[CH] = ddr``CH;

if i use it like:

`CONNECT(signal_list, 2)

then every thing is O.K and this macro replaced by:

   assign sginal_list[2] = ddr2;

But the problem start when i am using it inside generate:

genvar c;
for (c = 0; c < 2; c = c+1) : test
begin
   `CONNECT(signal_list, c)
end
endgenerate

I get the next code:

assign sginal_list[0] = ddrc;
assign sginal_list[1] = ddrc;

i expect to get ddr0 & ddr1 and not ddrc
Any idea?
Thanks

2

Macros are pre-processor compiler directives. That means macros are processed before any Verilog syntax is parsed - before the compile knows about the generate statement.

Your choices are:

  • fix the ddrN code to be an array in the first place
  • manually write the code
  • find another pre-processor that can handle the looping macro code.
3

In reply to dave_59:

Thanks.
I cant change the ddrN to be array (its not my code)
1 can write it manually but its a lot of work.
although Macros are pre-processor compiler directive. surprisingly it did work for the left side.
is there any other way to get the desied code by using system verilog only?
Thanks

4

In reply to kobipinhas:

After the macro processing, the generate statement looks like

genvar c;
for (c = 0; c < 2; c = c+1) : test
begin
   assign signal_list[c] = ddrc;
end

There is no way to get this to work within SystemVerilog except by manually writing the code. Perhaps you can use a text editor macro to help you.