Define from one package are visible in another package

SystemVerilog
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1

For a change, I am posting query for thing which seems working when I didn’t expected them to.

defs.d:
`define WIDTH 3

p1.sv:
package p1;
`include “defs.d”
endpackage

file.sv:
bit[`WIDTH-1:0] var;

p2.sv:
package p2;
import p1::*;
`include “file.sv”
endpackage

As I understood with both p1 and p2 having different compilation scope, this should have resulted in error when any `define mentioned in defs.d gets referred in file.sv.

But above thing is working fine, is this expected?

2

In reply to bhupesh.paliwal:

Section 3.12.1 of the LRM discusses compilation units. It is a requirement that tools support both single file compilation unit and multi-file compilation unit. The behavior you are seeing is when multi-file compilation unit is used, which is the default behavior for some tools. Other tools default to single file compilation unit.

3

In reply to cgales:

Actually I referred to some old post where similar has been discussed : Compilation Issue from define in package | Verification Academy

Accordingly as I understand `define/macros are likely to be pre-processed before compilation can begin. When compilation of package p2 start, WIDTH is not likely to be visible … isn’t it?

4

In reply to bhupesh.paliwal:

You need to confirm that p1.sv and p2.sv are being compiled as separate compilation units. If they are being compiled as a single compilation unit, although it looks as if the macro name is being imported, that is not the case. Macro names do not belong to any scope.

Here’s another experiment you can try

file A.sv:

package A;
`define WIDTH 5;
endpackage

file B.sv:

package B;
`define WIDTH 10;
endpackage

file top.sv

module top;
  import A::*;
  import B::*;
  initial $display(`WIDTH);
endmodule

Try changing the order of compiling A.sv and B.sv, as well as the ordering of the import statements to see if it makes any difference.

5

In reply to dave_59:

In my VCS command both p1.sv and p2.sv files are going as part of file-list supplied with -f option i.e.
file.list:
p1.sv
p2.sv
rtl.sv

On VCS command:
vcs +vcs+lic+wait -sverilog +incdir+src -f file.list

I might be having little understanding on compilation scope, but for me as I understand in above each entry in file.list we create it’s own scope … i.e. p1.sv and p2.sv will have their separate scope and in similarly if some additional rtl.sv is there it will have it’s another compilation scope. Have wrongly understood this?

6

In reply to bhupesh.paliwal:

Yes, you have misunderstood. Different tools have different defaults for handle compilations scopes. Any tools that compiles the code you wrote as a single compilation unit will not produce an error and has nothing to do with packages. Try experimenting with the code I gave you.

7

In reply to dave_59:

Thanks Dave,

I tried

it matters the order of compilation

order of imports does not make any difference.

8

In reply to anoopjmd:

In reply to dave_59:
Thanks Dave,
I tried
it matters the order of compilation
order of imports does not make any difference.

It matters that you have compiled a package before it can be imported. But the issue here was with compiler directives, which has nothing to do with packages or importing them.