Define from one package are visible in another package

SystemVerilog
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4

In reply to bhupesh.paliwal:

You need to confirm that p1.sv and p2.sv are being compiled as separate compilation units. If they are being compiled as a single compilation unit, although it looks as if the macro name is being imported, that is not the case. Macro names do not belong to any scope.

Here’s another experiment you can try

file A.sv:

package A;
`define WIDTH 5;
endpackage

file B.sv:

package B;
`define WIDTH 10;
endpackage

file top.sv

module top;
  import A::*;
  import B::*;
  initial $display(`WIDTH);
endmodule

Try changing the order of compiling A.sv and B.sv, as well as the ordering of the import statements to see if it makes any difference.