Use of if/else conditions around assign statements in Macros

SystemVerilog
,
1

Hi,

I am trying to use a Macro to assign signals based upon certain values as passed to Macro, but run into errors. This is an example code.
I have tried using generate / gevar within macro, but same error. It works without if statement, but doesn’t solve the intent.


`define LBsig_IF(i) \
begin \
   if(i == 1) \                            
      assign sig_``i``_ip = if_sig[``i``+1]; \
   else if(i == 3) \                            
      assign sig_``i``_ip = if_sig[``i``+2]; \
   end \
end          

module test;
  int sig_1_ip, sig_2_ip, sig_3_ip;
  int if_sig[10];

  `LBsig_IF(1)

  initial begin
     if_sig[0] = 1;
     if_sig[1] = 1;
     if_sig[2] = 1;
     if_sig[3] = 1;
     if_sig[4] = 1;
  end
endmodule

**
Error:**
Error-[SE] Syntax error
Following verilog source has syntax error :
“test.v”, 20: token is ‘assign’
assign sig_i_ip = if_sig[i+1];
^

2

In reply to ajanjua:

This thread should answer your question.

3

How is this scenario finally resolved?
I am trying out something similar in my testbench, but seeing cross-module reference compilation errors.
The “thread” link above does not seem to direct to exact thread which discusses the resolution.

4

In reply to rjoshi10:

Don’t know what happened to that thread, but this code had a few typos. Remove the begin/end/end within the macro, and all the trailing spaces after the 's