I hope to not bother, but for the first time I am approaching the world of the Verification by using System Verilog and I have learnt about the TB components only recently (Generator, Driver, Monitor etc). My actual task right now is to realize a testbench in SV, creating all those components, for an Asynchronous FIFO, which you can find at the following link:
I know when it comes to realize a testbench in Verilog for a design, I should only focus on the top_level of the design, even if there are multiple modules instantiated inside, but since now I need to realize the Transaction class, the Scoreboard etc I would like to be sure on what I need to focus to be honest.
Thanks whoever is going to answer me, wish you a good day.
I implemented Cummings asyn fifo in my book in both VHDL and Verilog.
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
should only focus on the top_level of the design, even if there are multiple modules instantiated inside, but since now I need to realize the Transaction class, the Scoreboard etc I would like to be sure on what I need to focus to be honest.
I see 2 questions here:
- The fifo as an IP. Thus, the verification can be done with SVA and a TB. I cover tassertions for a FIFO in my SVA 4th edition.
- SInce the fifo is in a subsystem, top level verification of data flow is needed