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During my years of contributions to the Verification Academy SystemVerilog Forum, I have seen many trends in real users’ difficulties in the application of assertions, and misunderstandings of how SVA works. In Part 1of this article, I addressed the difficulties in expressing requirements for assertions, and clarified some critical SVA concepts concerning terminology, threads, and vacuity.
In Part 2 of this article, I will address the usage of these four relationship operators: throughout, until, intersect, implies.
OPERATORS: THROUGHOUT, UNTIL, INTERSECT, IMPLIES
Sequences that use the keywords throughout and intersect describe the relationship between sequences. The until ( s_until, until_with, s_until_with) describes a tight
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