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In my years of contributions to the Verification Academy SystemVerilogForum, I have seen trends in real users’ difficulties in the application of assertions, the expression of the requirements, the angle of attacks for verification, the misunderstandings of how SVA works, and the confusion as to which SVA option to use.
In this first episode on the Verification Horizons, I am addressing two aspects of users' difficulties with SVA dealing with 1) expressing requirements for assertions; 2) SVA concepts concerning terminology, threads, and vacuity. In future episodes, I’ll address topics related to 1) the usage of these four relationship operators: throughout, until, intersect, implies ; 2) workarounds of illegal SVA operations such as
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