Browse all content in Verification Academy: Articles, Cookbooks, Resources, Sessions, and Tracks

Welcome to the DVConUS 2022 issue of Verification Horizons. As I may have mentioned previously, I am an avid golfer. Unfortunately, since I live in Massachusetts, my golfing opportunities this time of year are somewhat limited. I will admit to having a putting mat in my home office that I use regularly, but I don’t have room to swing any of my other clubs. As a result, it usually takes me some time at the beginning of each season to get my swing back in a groove. On top of that, I was unable to improve my scores last year as much as I had hoped, so this winter, I’ve adopted a new strategy: simulation!

That’s right. I’ve actually figured out how to relate my golf game to functional verification. As we know, if you can’t detect a problem, you can’t fix it. And if you can’t measure something, you can’t improve it. So, just as we have simulators and other tools for functional verification, I started using a simulator and taking lessons to improve my golf game. A new indoor golf facility just opened near my house, so now I can not only hit balls every weekend, but the simulator tracks and measures every aspect of my swing, so I know what I need to improve. I have learned two very important lessons. The first is that I am doing things of which I was unaware. The second is that there are some things I thought I was doing, but it turned out that I was doing something else. I won’t bore you with the details, but I have managed to add distance and accuracy (when I swing correctly) to my shots, which is the whole point. Being able to hit regularly over the winter and see my progress has me excited for the coming season.

As always, we have a great slate of articles in this issue that I hope you’ll find similarly enlightening. In our first article, “NVMe-oF – Simple, Invisible Fabric to Cloud Storage,” we learn some of the advantages of the new NVMe-OF (Non-Volatile Memory Express Over Fabrics) protocol for memory-intensive applications, allowing faster and more efficient connectivity between storage and servers while reducing CPU utilization on the host servers. As with anything, these advantages come at the cost of additional verification complexity, so we’ll also see how the NVMe-OF QVIP component can help you build a verification environment to handle these issues.

Our new Visualizer Debug Environment gives you a unified user interface to all our functional verification tools. So, no matter which tool you’re using, you’ll find “Getting to Know Visualizer” to be a really useful introduction to this important tool. In fact, there’s so much to tell you about Visualizer we could only include Part One in this issue. Be sure to come back to our next issue in July to see what else Visualizer can do for you. In the following two articles, we’ve partnered with some of our friends to share some ideas on achieving DO-254 compliance. In “Enabling Model-Based Design for DO-254 Certification Compliance,” our friends at MathWorks discuss a Model-Based workflow driven by requirements that uses Simulink and Questa together to take you from concept through the implementation of a DO-254-compliant project. In “How Do You “Qualify” Tools for DO-254 Programs?” our friends from Patmos Engineering Services walk us through the complicated process to qualify a tool to be used in a DO-254 project. As you’ll see, the advantage of having DO-254 specialists like Patmos as partners is that we’ve already qualified our tools, so at any step of a DO-254 project, you can be confident that your Siemens EDA tool is the right tool for the job.

We switch gears a bit and bring you “Reflections on Users’ Experiences with SVA” from our friend and noted SystemVerilog Assertions expert Ben Cohen. Ben was kind enough to share his thoughts on some of the “gotchas” that he’s seen over the years. In Part One (Part Two will be in the July issue), we’ll see what Ben recommends for expressing requirements for assertions and learn some critical SVA concepts and terminology.

Our friends at Bitec will show us “A Faster Approach to Co-Simulation Using Questa and VPI.” I love articles like this because I actually did a rudimentary version of this many years ago as a young engineer. Of course, the problem has changed dramatically over the years. As you know, we need to run software, which defines a substantial portion of the overall system functionality, but for the most part, simulating the actual CPU model is unnecessary overhead. Bitec has developed a unique VPI library that works with their VIP to solve this problem.

Last but not least, our friends at EmLogic introduce us to “UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification.” As you all know, I’m a huge SystemVerilog and UVM fan. But to my amazement (NOTE: this is sarcasm), there are still engineers who prefer VHDL. Well, UVVM brings many of the advantages of structured modular, reusable verification components from UVM to the VHDL community. This brief overview will introduce you to this new verification library and show you how it can make your VHDL verification efforts more effective and efficient.

So, while I work on improving my golf game, I hope that you all will find something in this issue of Verification Horizons to improve your verification game. While it’s unlikely that I’ll be out on the golf course before you read this, I hope to continue getting positive results from the simulator. You’ll have to wait for the DAC issue in July to hear if that translates to the course.

Respectfully submitted,
Tom Fitzpatrick
Editor, Verification Horizons