UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification
Verification takes half of a typical FPGA project’s development time. It is possible to significantly reduce this time with only minor adjustments and no extra cost while dramatically increasing the ability to reuse testbench components.
An FPGA design’s architecture – from the top to the microarchitecture – is critical for both the FPGA quality and the development time. The same is true of the testbench.
