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Verification takes half of a typical FPGA project’s development time. It is possible to significantly reduce this time with only minor adjustments and no extra cost while dramatically increasing the ability to reuse testbench components.
An FPGA design’s architecture – from the top to the microarchitecture – is critical for both the FPGA quality and the development time. The same is true of the testbench. For example, the open-source UVVM (the Universal VHDL Verification Methodology) reduces the verification time significantly while at the same time improving testbench reuse and product quality.
UVVM provides the best VHDL testbench approach possible. Its straightforward and powerful architecture allows designers to build test harnesses
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