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Co-simulating systems, including RTL and software, may often require excessive computational times if a cycle-accurate CPU model is used. However, many co-simulation exercises do not necessarily require precise CPU models and may benefit from the solution proposed here.
This article presents a not-widely-used method of co-simulation that doesn’t need a cycle-accurate CPU simulation model and reduces simulation time while still allowing functional testing of software and RTL.
A newly designed library uses VPI hooks offered by Questa to bridge together DUT’s RTL and software, allowing emulating the whole system without the CPU model overhead.
We will demonstrate the proposed technique using the Bitec DisplayPort IP and its API software
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