The Visualizer Debug Environment is the user interface to debug, analyze and verify all our functional verification tools.
Visualizer is first and foremost a waveform debugger. It also includes source code debug, transaction debug, C debug, driver tracing, X tracing, schematics, glitch debug, low power debug, and coverage analysis and coverage debug – all supporting Verilog, SystemVerilog, VHDL, System C, and C/C++. It supports debugging simulation with Questasim, emulation with Veloce, and prototyping with VPS.
Visualizer supports live simulation debug and post-simulation debug.
HOW TO GET STARTED
You can find many resources on the Siemens Support Centerwebsite. Choose Visualizer and start with “Learn and Explore.”There are many short