Topics tagged packed

Topic	Replies	Views	Activity
How to OR a Dimension of a Multi-Dimensional Packed Array SystemVerilog SystemVerilog , for-loop , 2-dimensional-array , packed	3	542	July 13, 2023
Assigning a packed type 'byte' to a string requires a cast SystemVerilog SystemVerilog , cast , packed	1	844	April 25, 2023
Packed dimension for integer vs. bit vector SystemVerilog SystemVerilog , packed	2	1503	December 22, 2021
Enums in packed data SystemVerilog SystemVerilog , enumeration-datatype , packed	6	3156	November 8, 2021
Packed logic array, signed/unsigned SystemVerilog SystemVerilog , logic , packed , unsigned	2	3282	December 2, 2020
Assigning Packed Type to Unpacked Type SystemVerilog SystemVerilog , testbench , packed , unpacked	3	3236	September 30, 2020

How to OR a Dimension of a Multi-Dimensional Packed Array

SystemVerilog , for-loop , 2-dimensional-array , packed

3

542

July 13, 2023

Assigning a packed type 'byte' to a string requires a cast

SystemVerilog , cast , packed

1

844

April 25, 2023

Packed dimension for integer vs. bit vector

SystemVerilog , packed

2

1503

December 22, 2021

Enums in packed data

SystemVerilog , enumeration-datatype , packed

6

3156

November 8, 2021

Packed logic array, signed/unsigned

SystemVerilog , logic , packed , unsigned

2

3282

December 2, 2020

Assigning Packed Type to Unpacked Type

SystemVerilog , testbench , packed , unpacked

3

3236

September 30, 2020