How to OR a Dimension of a Multi-Dimensional Packed Array

SystemVerilog
, , ,
1

I have 64 bytes in a multi-dimensional packed array. I want to OR bits of every byte and return a 64 bit result, where each bit represents the OR result of 8 bits in a byte. I wrote a snippet below. Would it work? Is it synthesizable? Could you recommend a better way?

It should be parametric, so I cannot go for manually ORing 8 elements.



module my_module #(
    localparam DEPTH = 64,
    localparam WIDTH = 8
)(
    input logic  [DEPTH-1:0][WIDTH-1:0] arr,  // Two dimensional input array
    output logic [DEPTH-1:0]            res   // One dimensional output array
);

always_comb begin
    // Default assignment:
    res = '0;

    for (genvar i = 0; i < DEPTH; i++) begin
        for (genvar y = 0; y < WIDTH; y++) begin
            res[i] = res[i] | arr[y];
        end
    end
end

endmodule
2

In reply to veli:

You cannot put a generate-for loop inside an always block. But you can put procedural-for loop inside an always block, or put an always block inside a generate-for loop. I think you wanted

always_comb begin
    // Default assignment:
    res = '0;
 
    for (int i = 0; i < DEPTH; i++) begin
        for (int y = 0; y < WIDTH; y++) begin
            res[i] = res[i] || arr[i][y]; // note arr index [i][y]
        end
    end
end
3

In reply to dave_59:

Thank you @Dave. Is this logic synthesizable in many tools?

4

In reply to veli:

Yes.