Packed logic array, signed/unsigned

SystemVerilog
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1
  1. When I have an array defined as such:
logic [7:0] log_arr;

Is it by default signed or unsigned?

  1. If I compare an unsigned logic array to zero, like this:
log_arr >= 0

this will always return true?

  1. If I compare an unsigned logic array to a negative integer, like this:
log_arr >= -1

what will happen?

Thanks!

2

In reply to Avi_311:

  1. logic, bit, reg, and packed arrays of those types are all unsigned by default.
  2. If log_arr is X or Z, the result will be 1’bx, otherwise the result is always true.
  3. Mixing signed and unsigned operands results in all operands treated as unsigned.

You should be able to try these experiments yourself on EDAPlayground.

Also, you should see this presentation on how Verilog expressions get evaluated.

3

In reply to dave_59:

Following question:
If I have

rand logic [7:0] log_arr_1;
rand logic [7:0] log_arr_2;

constraint smaller_than_5{
      log_arr_1 + log_arr_2 < 5;
}

Is there a possibility of overflow? meaning, would this be allowed by the constraint?
log_arr_1 == 'b11111111
log_arr_2 == 'b00000001