Packed logic array, signed/unsigned

SystemVerilog
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2

In reply to Avi_311:

  1. logic, bit, reg, and packed arrays of those types are all unsigned by default.
  2. If log_arr is X or Z, the result will be 1’bx, otherwise the result is always true.
  3. Mixing signed and unsigned operands results in all operands treated as unsigned.

You should be able to try these experiments yourself on EDAPlayground.

Also, you should see this presentation on how Verilog expressions get evaluated.