Multi-threaded UVM Testbench

Is UVM capable of creating a multi-threaded testbench. Here multi-core enabled multi-threading is not questioned.
And if UVM is capable of such multithreading testbench creation then in what manner? Confused about multi-threading and UVM in the same frame.

The thread of a Verilog or SystemVerilog simulating hardware should not be confused with the thread of a single or multi-core processor running software. Although they are similar conceptually, they are represented differently. The implementation of a SystemVerilog simulator normally does not even use thread packages provided by the operating system.

The thread created by a simulation represents a process that can independently wait (or block) for a particular event. An event can be the change of a signal, or the passing finite amount of simulated time. The UVM manages all of your uvm_component classes by created threads for each component that can independently block waiting for particular events.

This is probably not going to answer your question completely, but you should research the scheduling mechanisms of Verilog for more information on how it manages threads.

In reply to dave_59:

So can we say that the threads in UVM testbench are normally the extended UVM components, sequences and the methods between fork and join.
As far I have searched such multi-threaded testbench will hardly make an impact on making the simulation time faster or the performance better unless the design is partitioned for multiple cores of the hardware. Is that so?