The thread of a Verilog or SystemVerilog simulating hardware should not be confused with the thread of a single or multi-core processor running software. Although they are similar conceptually, they are represented differently. The implementation of a SystemVerilog simulator normally does not even use thread packages provided by the operating system.
The thread created by a simulation represents a process that can independently wait (or block) for a particular event. An event can be the change of a signal, or the passing finite amount of simulated time. The UVM manages all of your uvm_component classes by created threads for each component that can independently block waiting for particular events.
This is probably not going to answer your question completely, but you should research the scheduling mechanisms of Verilog for more information on how it manages threads.