// Code your design here
module register_control #(parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 8,
parameter WAIT = 0
)
(pclk, presetn, psel, penable, pwrite, paddr, pwdata, prdata, pready, pslverr, tdr_reg, tcr_reg, tsr_reg, s_ovf, s_udf);
input wire pclk;
input wire presetn;
input wire psel;
input wire penable;
input wire pwrite;
input wire [ADDR_WIDTH-1:0] paddr;
input wire [DATA_WIDTH-1:0] pwdata;
output reg [DATA_WIDTH-1:0] prdata;
output reg pready;
output reg pslverr;
input wire s_ovf;
input wire s_udf;
output reg [DATA_WIDTH-1:0] tdr_reg;
output reg [DATA_WIDTH-1:0] tcr_reg;
output reg [DATA_WIDTH-1:0] tsr_reg;
localparam IDLE = 2'b00,
SETUP = 2'b01,
ACCESS = 2'b10;
reg [WAIT-1:0] wait_signal;
reg [1:0] current_state;
reg [1:0] next_state;
always @(*) begin
case(current_state)
IDLE: begin
wait_signal = WAIT + 1;
pready = 1'b0;
pslverr = 1'b0;
if(psel & ~penable) begin
next_state = SETUP;
end else begin
next_state = IDLE;
end
end
SETUP: begin
if(psel & penable) begin
if(wait_signal == 0) begin
pready = 1'b1;
if(paddr > 8'h07) begin
pslverr = 1'b1;
end
next_state = IDLE;
end else begin
next_state = ACCESS;
end
end else begin
next_state = SETUP;
end
end
ACCESS: begin
if(wait_signal != 0) begin
next_state = ACCESS;
end else begin
pready = 1'b1;
if(paddr > 8'h07) begin
pslverr = 1'b1;
end
next_state = IDLE;
end
end
default:
next_state = IDLE;
endcase
end
always @(posedge pclk or negedge presetn) begin
if(~presetn) begin
current_state <= IDLE;
end else begin
current_state <= next_state;
wait_signal <= wait_signal - 1;
end
end
always @(posedge pclk or negedge presetn) begin
if(~presetn) begin
tdr_reg <= 8'h00;
tcr_reg <= 8'h00;
tsr_reg <= 8'h00;
end else begin
if(pready & psel & penable & pwrite) begin
////////////////////
tdr_reg <= (paddr == 8'h00) ? pwdata : tdr_reg;
tcr_reg <= (paddr == 8'h01) ? pwdata : tcr_reg;
if(paddr == 8'h02) begin
// if(tsr_reg[1] && pwdata[1]) tsr_reg[1] <= 0;
// else if (tsr_reg[0] && pwdata[0]) tsr_reg[0] <= 0;
// else begin
// tsr_reg[0] <= tsr_reg[0];
// tsr_reg[1] <= tsr_reg[1];
// end
// tsr_reg[DATA_WIDTH-1:2] = pwdata[DATA_WIDTH-1:2];
if((tsr_reg[0] & tsr_reg[1]) & (~pwdata[0] & ~pwdata[1])) begin
tsr_reg[1:0] <= 2'b11;
end else begin
tsr_reg[1:0] <= 2'b00;
end
tsr_reg[DATA_WIDTH-1:2] = 0;
end
////////////
end else if(pready & psel & penable & ~pwrite) begin
case(paddr)
8'h00: prdata <= tdr_reg;
8'h01: prdata <= tcr_reg;
8'h02: prdata <= tsr_reg;
endcase
end else begin
tdr_reg <= tdr_reg;
tcr_reg <= tcr_reg;
tsr_reg <= tsr_reg;
end
end
always @(s_ovf or s_udf) begin
tsr_reg[0] = s_ovf;
tsr_reg[1] = s_udf;
end
endmodule
It would be helpful to display the exact error message, including the reported line. It’s most likely that you have an unbalanced set of begin/end statements.
1 Like
Thank you @dave_59. This is the error.
[2025-06-12 16:23:59 UTC] xrun -Q -unbuffered '-timescale' '1ns/1ns' '-sysv' '-access' '+rw' design.sv testbench.sv
TOOL: xrun 23.09-s001: Started on Jun 12, 2025 at 12:23:59 EDT
xrun: 23.09-s001: (c) Copyright 1995-2023 Cadence Design Systems, Inc.
always @(s_ovf or s_udf) begin
|
xmvlog: *E,NOTSTT (design.sv,132|7): expecting a statement [9(IEEE)].
xmvlog: *W,NOTOPL: no top-level unit found, must have recursive instances.
xrun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
TOOL: xrun 23.09-s001: Exiting on Jun 12, 2025 at 12:23:59 EDT (total: 00:00:00)
Exit code expected: 0, received: 1
The line 132 is always @(s_ovf or s_udf) begin.
Yeah. I fixed the error. Like you said, I got unbalanced set of begin end statements.