Part vector selection

[ashish_saroj]

Hello Guyss,

i need range out as variable from a and b but showing error please have look in it and provide solution.

module tb();
reg [5:0] a=5;
reg [5:0] b=10;
reg [20:0] out;

initial begin
out[b:a] = 7;
$monitor(out);
end

endmodule

[dave_59]

Using variable instead of hard coded bits

In reply to anupshet09: SystemVerilog does not allow part selects of a packed array to have a variable width. What most people do that is synthesizable is a shift and mask dt = (my_data >> endbit) & (32'hFFFFFFFF << (startbit - endbit + 1)) You could also use a for-loop to assign bit-by-bit for (ii=endbit,jj=0; ii<=startbit; ii++,jj++) dt[jj] = my_data[ii];

[ashish_saroj]

not this solution
suppose i want to send byte by byte data
i can use a[i+:8]=b; it is working
but my case is i want to write 50 bytes some times 45 some times 33 its depend on user
then how i can write memory logic for this

[dave_59]

That is completely new information. You have a memory (unpacked array), and you want to work in 8-bit bytes. It would help if you show us declarations for everything you are working with.