Using variable instead of hard coded bits

SystemVerilog
2

In reply to anupshet09:

SystemVerilog does not allow part selects of a packed array to have a variable width. What most people do that is synthesizable is a shift and mask

dt = (my_data >> endbit) & (32'hFFFFFFFF << (startbit - endbit + 1))

You could also use a for-loop to assign bit-by-bit

for (ii=endbit,jj=0; ii<=startbit; ii++,jj++)
   dt[jj] = my_data[ii];