Case statement range

SystemVerilog
1

Hello,

my scenario is dccc variable get randomze and generate between range 'h80 to 'h100 and in driver i am using:

 case(req.dccc) 
  req.dccc with {item inside {['h80:'h90]}: begin
                                                                         dccc_detect;         //task called
                                                                         end
  req.dccc with {item inside {['h90:'h100]}: begin
                                                                         dccc_send;         //task called
                                                                         end

i want solution for this logic which is not working properly hoping best solution on this…

2

We don’t know what “working properly” means. The code shown makes no sense (there is no randomization)

Show us a minimal, complete reproducible example

3

its coming random value from sequence i want that in case this type of syntax is valid or not ?

4

Not valid syntax.