What happens when we assign a value to a net at the time of declaration?

SystemVerilog
1

module test;

wire [0:3]a = 12 ;

initial
begin
$monitor(“the value of a is %d”,a);
$display(“the value of a is %d”,a);
end
endmodule

I Know that values to nets are continuously driven by continuous assignments. I was playing around and I found this error. Now according to my understanding the default value of net is high impedance . So when I try to use $monitor and $display to print the value , I should get high impedance but what i am getting is , when I use $display I get the value as unknown(x) and when I use $monitor I get the value which I have assigned .Can someone explain me what exactly is going on ?

/////////////////////////////////////////////////
this is the result I am getting

# the value of a in $display is ----->   x
# the value of a in $monitor is ----->  12

///////////////////////////////////////////////

2

$monitor prints values at the end of the time slot (postponed region).

In this example, the execution of the $display in the initial block and the first evaluation of the continuous assignment is a race condition.

The default value of an undriven wire is z(high impedance). However, the LRM does not specify what the initial value of a wire is.

3

thanks for replying @dave_59 . I still have one doubt. As the net data type does not store any value ,shouldn’t the monitor as well print nothing , as it is executed at the end of the time slot . My logic is the assignment is made at 0th simulation time and the monitor is executed at the end of the time slot , so shouldn’t the monitor print unknown(x) or default value of net data type , that is high impedance (z).

4

A net always has a resolved value. The continuous assignment and the initial block both execute in the active region of time 0. $monitor evaluates and prints its arguments values at the end of the time slot.

5

So , does this mean that internally Net data type also stores the value ?