Is it illegal/not recommended that the RHS of an inferred FF should not change in Active region along with Clock of the FF?

SystemVerilog
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1

Hi everyone,

I recently received a recommendation that RHS of an inferred FF and clock of the inferred FF should not change in active region.
However, in my opinion if the RHS is a wire/logic which is assigned using a BA the RHS will change in Active region.

Any documented/undocumented guideline is welcome.

Regards,
Prashant

2

In reply to prashantg:
You need to read up on non-blocking assignments.

RTL code is usually written with zero delays. If you have two always instances waiting on the same clock edge where one is writing (LHS) and the other is reading (RHS), then you have a race condition because you don’t know if the reader is seeing the old or new value. Everything executes in the active region.

When using non-blocking assignments, the writer postpones the update until the next active region so reader is now guaranteed to see the old value. Unfortunately, Verilog leave it up to the user to deal with it manually.