How to pass an array in verilog funcion

can any one help me passing an array to a function using verilog.


module x;
  integer x1;
  function func (ref integer a[]);
    $display ("%p", a);
  endfunction
 
  initial begin
    integer a [];
    a = {1,2,3,4,5};
    x1=func(a);
  end
endmodule 

Error-[SE] Syntax error
Following verilog source has syntax error :
“design.sv”, 46: token is ‘integer’
function func1 (ref integer a);

In reply to sambasiva:

Function with ref arguments shall be automatic - your function inside module is static by default.

In reply to Srini @ CVCblr.com:

Also, no need to use ref unless you plan on modifying the array and the array is very large. Use input, output, or inout.

In reply to Srini @ CVCblr.com:

In reply to sambasiva:
Function with ref arguments shall be automatic - your function inside module is static by default.

thank you for educating on this. Learning is always a never-ending action.
module x;
integer x1;
function automatic func (ref integer a);
$display (“%p”, a);
endfunction

initial begin
  integer a [];
  a = {1,2,3,4,5};
  x1=func(a);
end

endmodule

In reply to Srini @ CVCblr.com:

thank you but it didn’t helped me

module x;
integer x1;
function automatic func1 (ref integer a);
$display (“%p”, a);
endfunction

initial begin
integer a ;
a = {1,2,3,4,5};
x1=func1(a);
end
endmodule

Error-[SE] Syntax error
Following verilog source has syntax error :
“design.sv”, 45: token is ‘integer’
function automatic func1 (ref integer a);

In reply to dave_59:

thank you dave, but can you please show me an example of passing an array to a function using “verilog”.

In reply to sambasiva:

In reply to Srini @ CVCblr.com:
thank you but it didn’t helped me
module x;
integer x1;
function automatic func1 (ref integer a);
$display (“%p”, a);
endfunction
initial begin
integer a ;
a = {1,2,3,4,5};
x1=func1(a);
end
endmodule
Error-[SE] Syntax error
Following verilog source has syntax error :
“design.sv”, 45: token is ‘integer’
function automatic func1 (ref integer a);

This seems to be simulator issue. It works for me.

In reply to nhp:

I think you are using system verilog

In reply to sambasiva:

that is true. I tried in verilog and got the error you mentioned.

I assumed sv as default.

In reply to dave_59:

My question is can we pass arrays to verilog function, if yes how , please help me with this.

In reply to dave_59:

My question is can we pass arrays to verilog function, if yes how , please help me with this.