How to pass an array in verilog funcion

SystemVerilog
, ,
5

In reply to Srini @ CVCblr.com:

thank you but it didn’t helped me

module x;
integer x1;
function automatic func1 (ref integer a);
$display (“%p”, a);
endfunction

initial begin
integer a ;
a = {1,2,3,4,5};
x1=func1(a);
end
endmodule

Error-[SE] Syntax error
Following verilog source has syntax error :
“design.sv”, 45: token is ‘integer’
function automatic func1 (ref integer a);