Non- Blocking assignments with Transport delay

SystemVerilog
,
1 
module tb;
  reg clk;
  
  initial clk=1'b0;
  
  always 
    begin
       clk<= #70 0;
       clk<= #30 1;
    end
  
  initial
    begin
    #800;
   $finish;
    end
  
  initial
    begin
      $dumpvars(1);
      $dumpfile("dump.vcd");
    end
  
endmodule

Hi,
On executing the above code the simulator gives the output as follows :
./run.sh: line 15: 7 Killed

I had some conclusions in my mind after checking this in the simulator but I ain’t sure if that’s the reason. Can someone tell me why does it behave like this on using a non-blocking assignment with transport delay?

Thanking You

2

In reply to sai_pra99:

Your always statement has no blocking delays, so it is an 0 delay infinite loop. The same two assignments get executed over and over again without giving the simulation a chance to advance time. Normally, assignments to clocks use blocking assignments.