Synthesizability of the following code

SystemVerilog
, , ,
1

Following is a module given .

  • Is the following code synthesizable?
  • If not, why , provide all issues?
  • If yes, what element can it represent?
  • Repeat the same where the data_out assignment inside the always block happens with blocking operator (=) instead of non blocking operator (<=).

Trying to understand the code.
Appreciate your response.
Thanks

module abc; 
reg [2:0] data_out; 
input data_in; 
input clk; 
input rst;

always @(posedge clk) begin
    if (!rst) begin
        data_out <= 3'b0; 
    end 
    else begin
        for (int i=0; i<3; i++) begin
            data_out[i] <= 1'b1;  
        end
        data_out[0] <= data_in;  
   end
end
endmodule