How to implement UVM testbench for DUT VHDL?

UVM
, ,
1

I have a VHDL dut and I want to build a UVM testbench, I want to know:
1- Can UVM work with VHDL design ?
2- Is it possible to use Modelsim Student Version or Vivado 2020 ?

2

In reply to Kiruth:

You ca implement always multi-language testbenches. This is also valid for UVNN environments.

3

In reply to chr_sue:

Thanks for this reply, but what simulator could I use ?
EDA playground doesn’t support VHDL dut for UVM testbench,
Which simulator should I use for mixed language?

4

In reply to Kiruth:

Did you tryout Edaplayground as mixed language?
Unfortunately I’m not familiar with free simulators.