Hey!
I am still learning VHDL and I wrote a priproity encoder code
but it gives me 8 errors
Here is the code
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity prienc is
port (
a : in STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC;
y :out STD_LOGIC_VECTOR (2 downto 0)
);
end prienc;
architecture archprienc of prienc is
begin
process(en,a)
begin
if( en='0' )then
y <= "000";
else
y <= "001" when a(1)= '1' else
"010" when a(2)= '1' else
"011" when a(3)= '1' else
"100" when a(4)= '1' else
"101" when a(5)= '1' else
"110" when a(6)= '1' else
"111" when a(7)= '1' else
"000";
end if;
end process ;
end archprienc ;
And the errors are
vhd(19): Illegal sequential statement. (this error is from line 19 to line 25)
vhd(29): VHDL Compiler exiting
I work with modelsim 10.4
Can anyone help me ?
Hi Rana3n. You don’t use the when…else form inside a process. You can either get rid of the process, or use the if…elsif…else form inside the process. There are examples of both for a priority encoder if you Google it.
In reply to Rana3n:
It has been a very long time that I wrote any VHDL code as I really prefer SystemVerilog over VHDL; SystemVerilog is more compact and provides many more features (IMHO); in addition, the use of SVA along with SystemVerilog is very powerful. Anyway, the battle between those two languages is always in debate, but SystemVerilog is very widely adopted and supported.
Having said that, your code misuse the “when” statement
VHDL 2008 LRM
9.5.1 Conditional signal assignments
conditional_waveforms ::=
{ waveform when condition else }
waveform [ when condition ]
case_statement ::=
[ case_label : ]
case expression is
case_statement_alternative
{ case_statement_alternative }
end case [ case_label ] ;
case_statement_alternative ::=
when choices =>
sequence_of_statements
The "waveform when condition" is not part of " sequence_of_statements"
A solution to your code:
process(en,a)
begin
if( en='0' ) then
y <= "000";
elsif (a(1)= '1') then y <= "001";
elsif (a(2)= '1') then y <= "010"; --
---
end if;
end process ;