Regarding Instance constants being static in System verilog

SystemVerilog
1

From LRM 8.19 : Constant class properties : However, an instance constant cannot be declared static because doing so would disallow all assignments
in the constructor

I didn’t get the explanation. Why it cant be static ?. We can have the constant as static and have it initialized in the constructor only right ? (my compiler ofcourse doesnt allow static instance constants)

2

An instance member of a class is simply a non-static member. Instances members of a class get created when calling the constructor. Static members get created as part of the declaration of the class type without calling the class constructor.