Doubts about recursion in Verilog and systemverilog static world

SystemVerilog
1

Hi There,

I am working on two different problems one

reduction of digits sum to single digit eg : 12345 => 1+2+3+4+5 => 15 => 1+5=> 6

module top;
  function int incr(int a);
    if(a/10 == 0)
      return a%10;
    else
    	return incr((a%10) + incr(a/10));
  endfunction
  initial
    begin
      $display("sum = %d", incr(1992));
      $display("sum = %d", incr(1876));
    end
endmodule

vcs output :
sum = 3
sum = 4
V C S S i m u l a t i o n R e p o r t

mentor output :# run -all # sum = 3 # sum = 4 # exit

xcelium output :
xcelium> run
sum = 3
sum = 4
xmsim:

another problem is factorial of a number

5 => 5x4x3x2x1 => 120

module top;
  function int factorial(int a);
    if(a != 1)
      begin
        return a * factorial(a-1);
      end
    else
      return a;
  endfunction
  initial
    begin
      $display("factorial = %d", factorial(5));
    end
endmodule

VCS : factorial = 1
V C S S i m u l a t i o n R e p o r t

mentor : # run -all # factorial = 120 # exit

factorial = 120
xmsim: *W,RNQUIE: Simulation is complete.

here my notion is, when ever I am calling function recursively that time I need to use automatic is my notation correct or not, can anyone please correct my intention.

2

A recursive or reentrant function or task should always be declared with an automatic lifetime. The evaluation order of operands is indeterminate and sometime you get lucky that the recursion works as your second example shows that is not always the case.