SystemVerilog Assertions Free/Symbolic Variable Usage Error

SystemVerilog
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1

Hello,
Is there any workaround to do this in system verilog?

logic [3:0] bank_sel;
logic [4:0] sram_sel;

property sram;
@(posedge clk) disable iff(!resetn)
sram_top.u_0.sram_col_inst[bank_sel].sram_row.cen[sram_sel]
|->
…
;endproperty
assert property(sram);

ERROR is:
illegal index value for ‘for-generate’

More info:
The dut is a sram memory and I am trying to use the free variable in the hierarchy to allow the tool to access sram’s randomly which are instantiated in generate for loops in the dut.

2

You can only access for-generate instances with constants. You can do that with another for-generate loop.

property sram(index);
  @(posedge clk) disable iff(!resetn)
  bank_sel == index && 
  sram_top.u_0.sram_col_inst[index].sram_row.cen[sram_sel]
  |->
   …
endproperty

for(genvar i=0;i<MAX_SEL;i++) begin : bank
   assert property(sram(i));
end
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