Specifying bit ranges of arrays in VCD

SystemVerilog
1

What is the motivation behind the following syntax for VCD (value change dump) files?:

Excerpt from Syntax 21-20—Syntax for output 4-state VCD file (LRM 2023)

reference ::= identifier 
                     | identifier [ bit_select_index ] 
                     | identifier [ msb_index : lsb_index ]

declaration_command ::= 
   ...
  | $var [ var_type size identifier_code reference ] $end 
  ...
size ::= decimal_number

I am also aware of the following limitations of VCD:

Unpacked arrays and automatic variables are not dumped.

I could not find any documentation in the LRM on what bit_select_index and [ msb_index : lsb_index ] are for. There is only an example using the range:

From 21.7.2.4 4-state VCD file format example:

$var reg 32 (k accumulator[31:0] $end

It seems like a bit vector, but it is not crystal clear from whether it is an packed or unpacked array.

Extended VCD file seems to take a different approach to indexes:

var_section ::= var_type size identifier_code reference
size ::= 1 | vector_index
reference ::= port_identifier

Page 699:

input [0:3] data;

=>

$var port [0:3] <2 data $end $var port 1 <3 reset $end

But I am confused about whether this part of the extended VCD syntax is only for ports. :confused:

Most of the VCD files I have seen before do not add bit_select_index or the range, because size seems to be enough to describe a vector. I also have seen that one waveform viewer uses the range, e.g., [4:-2], to parse the decimal bits of a fixed number to represent the value of a fixed number. Maybe bit_select is used to dump the individual values of an unpacked vector, because of the above limitation of the VCD format.

  1. What is the actual motivation for bit_select_index and the range?
  2. When must these (bit_select_index and the range) be used? Or are these just optional?
  3. Does the extended VCD ditch bit_select_index and the range and use the size for ranges?
2

The standard for VCD and extended VCD was established by attempting to emulate the behavior of underspecified tools.

Signals in VCD are always packed vectors. Tools have the option of dumping signals as individual bits using bit_select_index or as an entire range [ msb_index : lsb_index ]. The choice between dumping individually or keeping them together depends on how optimizations affect the signal’s representation.

The size in an eVCD port must be either 1 or [ msb_index : lsb_index ]. You cannot dump port bits individually.

3

So I understand that the standard became whatever most tools did without clarifying the different interpretations :smiling_face_with_tear:.

Tools have the option of dumping signals as individual bits using bit_select_index or as an entire range [ msb_index : lsb_index ]

Now I see this also in the LRM, thanks:

691:

c) The individual bits of vector nets can be dumped individually.

You cannot dump port bits individually.

Suddenly I noticed that too :slightly_smiling_face::

698:

The extended VCD format does not support a mechanism to dump part of a vector. For example, bits 8 to 15 ([8:15]) of a 16-bit vector cannot be dumped in VCD file; …

I still have the following doubts:

  1. Some waveform viewers use [4:-2] to specify the components of a fixed-point number that has the size of 7 bits. Even though this dumps all the bits, it does not violate the VCD spec, right?
  2. Does the eVCD syntax only apply to ports? (even the LRM states only the following differences in the introduction:)

… The following two types of VCD files exist:
a) 4-state: to represent variable changes in 0, 1, x, and z with no strength information.
b) Extended: to represent variable changes in all states and strength information.

4

In the section about creating an extended VCD file, the LRM says

The $dumpports task shall be used to specify the name of the VCD file and the ports to be dumped. So yes, it only applies to ports.

The conventions tools use to display fixed point notation is independent of VCD and a tool specific feature. This Siemens sponsored public forum is not for discussing tool specific issues. Please read your tool’s User Manual or contact your tool vendor for support.

1 Like
5

Thanks for answering 2.

I believe my first question was not clear. I will try to formulate it in a more practical way:

Different tools may have different conventions, however the LRM does not imply any difference between the following two statements, no?

$var wire 5 $ signal $end
$var wire 5 $ signal[2:-2] $end