Multiclock Assertion

SystemVerilog
1

Hi,

I want to write a assertion so that at a posedge of clock 1 check for negedge of signal a if this condition satisfied then at negedge of clock 2 signal b should be low for 2 clock Cycles.

If any condition failed assertion fails, can anyone help me to achieve this?

Thanks

2

Use this as a start. It is not correct
https://www.perplexity.ai/search/i-want-to-write-a-assertion-so-5BLZ.aIDTZSClYwweaSglg

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3

See last request at
https://www.perplexity.ai/search/i-want-to-write-a-assertion-so-5BLZ.aIDTZSClYwweaSglg

property b_low_for_2_clk2_cycles_after_a_fall;
  @(posedge clk1)
    $fell(a) |=> 
      @(negedge clk2) (b == 0)[*2];
endproperty

assert property (b_low_for_2_clk2_cycles_after_a_fall)
  else $error("Multiclock assertion failed: b was not low for 2 negedge clk2 cycles after a fell at posedge clk1");