Illegal assignment mailbox error

SystemVerilog
1

Kindly help to resolve the basic stuff of mailbox error.

Transaction class:

class transaction;
   rand bit [7:0] data;

function void display();
      $display ("[%0t] Data = 0x%0h", $time, data);
   endfunction
endclass

Generator class:

class generator;
`include "transaction.sv"
   mailbox mbx;

   function new(mailbox mbx);
      this.mbx = mbx;
   endfunction

   task genData();
      transaction trns = new();
      void'(trns.randomize());
      void'(trns.display());
      $display ("[%0t] [Generator] Going to put data packet into mailbox", $time);
      mbx.put(trns);
      $display ("[%0t] [Generator] Data put into mailbox", $time);
   endtask
endclass

driver class:

class driver;
`include "transaction.sv"
   mailbox mbx;

   function new(mailbox mbx);
      this.mbx = mbx;
   endfunction

   task drvData ();
      transaction drvTrns = new();
      $display ("[%0t] [Driver] Waiting for available data", $time);
      mbx.get(drvTrns);
      $display ("[%0t] [Driver] Data received from Mailbox", $time);
      void'(drvTrns.display());
   endtask
endclass

tb top module:

module tb;

`include "transaction.sv"
`include "generator.sv"
`include "driver.sv"

   mailbox mbx;
   generator Gen;
   driver    Drv;

   initial begin
      mbx = new();
      Gen = new(mbx);
      Drv = new(mbx);

      fork
         #5 Gen.genData();
         #10 Drv.drvData();
      join_none
   end
endmodule

It is not runnning.

2

What do you mean by ‘not running’? Does it compile? Does it elaborate? Does it run but give an error? Does it run but not give the results you expect?

You should provide more detail regarding your issues and design requirements.

Also, it would really help to have a minimal, complete reproducible example, preferably on EDA Playground.

3

Hi Cgales,

It is compiling. No syntax error. But it gives the fatal error as given below:

[0] [Driver] Waiting for available data

[10] Data = 0x50

[10] [Generator] Going to put data packet into mailbox

[10] [Generator] Data put into mailbox

** Fatal: Illegal assignment to class work.tb/work.driver::transaction from class work.tb/work.generator::transaction

Time: 10 ns Iteration: 1 Process: /tb/fork#18_4f5f3030 File: C:/questasim64_2021.1/win64/…/verilog_src/std/std.sv

Fatal error in Task std/mailbox::get at C:/questasim64_2021.1/win64/…/verilog_src/std/std.sv line 41

HDL call sequence:

Stopped at C:/questasim64_2021.1/win64/…/verilog_src/std/std.sv 41 Task std/mailbox::get

called from driver.sv 12 Task tb/driver::drvData

called from tb.sv 18 Module tb

4

When you include a file inside a class, you create a specialization that doesn’t match the other classes where the file is included. You should look at the SystemVerilog LRM and use packages as appropriate.

5

Thanks. It is working now.