Assertion to find the difference between two clocks

SystemVerilog
1

HI All,

consider the following property to find a glitch

  property p1(clk);
  realtime first_change;
    @(clk)
    ('1, first_change=$realtime)|=>$realtime-first_change>=2ns;
  //time period between 0->1 and 1->0 should not be less than 2ns, if yes its a glitch. 
  endproperty

Keeping the same concept in mind, Now i have written the assertion
to find the difference between two clocks in terms of freq or time duration.

If clk1 is 100mhz, that is 10ns, clk2 should also be the same.
In case if there is a difference, assertion should fail

This is the following code, its not working as expected.
Assertion is failing for every clock, even though I have generated the same clock

module two_clk_assertion;
  logic clk1, clk2;
  
  property p1(clk1, clk2);
  realtime first_change;
    @(clk1)
    ('1, first_change=$realtime)|=>$realtime-first_change==clk2;
endproperty

  
  L1: assert property (@(posedge clk1) p1(clk1, clk2))
    $display("TIME: ====FPV PASS=====", $time); 
    else
    $display ("**FPV FAIL**");
 
    initial begin
      clk1=0;
      clk2=0;
      #100 $finish;
    end
    
  	initial forever #5  clk1 = ~clk1;
  	initial forever #5  clk2 = ~clk2;
  
    initial begin
      $dumpfile("dump.vcd"); $dumpvars;
    end
    
endmodule

Kindly suggest how can I modify or update the code to find the difference in two clocks.

Thank you,

2

The code you provided will always result in $realtime-first_change being 5 and clk2 being either 0 or 1. Consequently, the assertion will always fail.