Check if the two clocks have the same phase

SystemVerilog
1

Hi sir,

I want to seek help on checking whether two clocks are in the same phase using SVA
2

In reply to icuser3:

Try the following


  always #5 clk1 = !clk1 ;
  always #5 clk2 = !clk2 ;
  always #6 clk3 = !clk3 ;
  
  property p1( cl1 , cl2 );
    realtime t1,t2;
    @(posedge cl1) (1,t1=$realtime) ##0 @(posedge cl2) (1,t2=$realtime) |->  ((t1-t2) == 0);
  endproperty  
  
  ap1:assert property( p1(clk1,clk2) ) $display("T:%0t Pass",$time); 
                                  else $display("T:%0t Fails",$time);
    
  ap2:assert property( p1(clk2,clk3) ) $display("T:%0t Pass",$time); 
                                  else $display("T:%0t Fails",$time);  
    
  initial begin
    #20;$finish();
  end