Bit Precision used during following assignment

SystemVerilog
1

Hi All,
Consider the following assignment ::

 parameter DEPTH;
 reg [$clog2(DEPTH)-1:0] w_ptr, r_ptr;

 assign full = ((w_ptr+1'b1) == r_ptr); // 1'b1 is 1-bit unsigned type

(Q1) I am curious to know if the explicit size cast of 1’ is required here ?
If I were to write

assign full = ((w_ptr+1) == r_ptr); // By default 1 is 32-bit signed type

My understanding is that all the RHS signals would use 32-bit precision (assuming both the pointers are less than 32-bits) with 0’s being padded to both the pointers

(Q2) Are both 1’b1 and 1 treated as 2-state type or 4-state type ?

2

(A1) Not required in the expression here, regardless of the width of the pointers.
(A2) 4-state types. All integer literals are considered have a packed array of logic datatype.