SV Property - Using an absolute 1ns delay

SystemVerilog
1

This works …

property clock_en(clk_in, gated_clk, clock_gate_en, delay);
@(negedge clk_in)
clock_gate_en |=> ##(delay) !$stable(gated_clk);
endproperty

I want the checking to begin 1ns after negedge clk_in.

This did not work for me …

property clock_en(clk_in, gated_clk, clock_gate_en, delay);
@(negedge clk_in) ##1ns
clock_gate_en |=> ##(delay) !$stable(gated_clk);
endproperty

How do I wait 1ns before doing " clock_gate_en |=> ##(delay) !$stable(gated_clk);" ?

Thanks!

2

I assume this works as ‘delay’ is an elaboration / compilation time integer constant.

I am not clear on the following ::
(1) Is the clock period for ‘clk_in’ independent of 1ns ? ( i.e it can be less than 1ns or equal to 1ns or even greater than 1ns )
(2) Should ‘clock_gate_en’ be sampled at 1ns after clocking event or at the clocking event after 1ns (where 1ns delay itself is calculated after an initial clocking event) ?