Constraint Solver error

SystemVerilog
1

I am unable to figure out what is wrong with following constraint. I get - Error-[CNST-CIF] Constraints inconsistency failure

class fin_array;
  rand bit[31:0] N[10];
  
  constraint c_N {
    
    foreach (N[i]){
      if (i >0)
      {
         N[i] == i;
        N[i+1] == i;
        //i == i +2 ;
      }
    }
     }
2

N[i+1] tries to access invalid Index ‘32’
Try using

foreach (N[i]){
  if ( i inside{[1:30] )
  {
     N[i] == i;
    N[i+1] == i;
    //i == i +2 ;
  }
}
 }
3

Thanks I did - but still the same error
foreach (N[i]){
if (i >0 && i < 30)
{
N[i] == i;
N[i+1] == i;
//i == i +2 ;
}
}

4

There are 2 other issues I missed ::
(1) Each bit of ‘N’ can be either 0 or 1 and you are trying to assign non-binary values ( 2 to 31 )
(2) There is a possible conflict when each index is being assigned twice
Eg: When i is 1, you constraint N[1] and N[2]
When i is 2, you constraint N[2] and N3]

N[2] is being constrained twice. If the constrained values are different there would be a conflict