Change instance reference using macro

SystemVerilog
,
2

This cannot be done for 2 reasons. First, macros are preprocessed before any thing else. It will create the following code:

 for(g=0; g<3; g++) begin
   assign a[g] = dut.u_a3.u_a2string'(g+97).u_a1.a;
 end

And u_a2string’(g+97) is not a valid instance path name.

Second, identifiers in SyatemVerilog are symbols, not strings that can be manipulated.