String concatenation inside generate block

SystemVerilog
, , , , ,
1

Hi,
I’m trying to simulate something like this:

`

define myreg(name) \
logic b_``name``_int;

generate 
for (genvar i=0; i<8; i++) begin

modulexyz xyz ( .a(a),
                .b(`myreg(i))
);

end
endgenerate

To the submodule xyz , the input b is to be passed with b_0_int , b_1_int ,… b_7_int . What is the best way of using the `define macro for this usage ?

The above , during the compilation gives b_i_int instead of b_0_int, b_1_int , etc.,.
I understand that `define are compiled earlier than the generate blocks. Then how should be above usage be coded ? I donot want to use an array as it adds a lot of code lines.

2

In reply to randomcoder:

You need to explain why you think using an array is more code.

Your alternatives are:

  • unrolling the generate loop manually
modulexyz xyz_0 ( .a(a),
.b(b_0_int));
modulexyz xyz_1 ( .a(a),
.b(b_1_int));
modulexyz xyz_2 ( .a(a),
.b(b_2_int));
modulexyz xyz_3 ( .a(a),
.b(b_3_int));
modulexyz xyz_4 ( .a(a),
.b(b_4_int));
modulexyz xyz_5 ( .a(a),
.b(b_5_int));
modulexyz xyz_6 ( .a(a),
.b(b_6_int));
modulexyz xyz_7 ( .a(a),
.b(b_7_int));
  • packing the variables into an array
wire [0:7] my_reg = {b_0_int,b_1_int,b_2_int,b_3_int,b_4_int,b_5_int,b_6_int,b_7_int};
generate
for (genvar i=0; i<8; i++) begin
modulexyz xyz ( .a(a),
.b(my_reg[i]
);
end
endgenerate
3

In reply to dave_59:
Hi dave,
Thanks for your quick response.

Each b_int is of say 256 bits, and say i have variables from b_0_int to b_127_int , I will have to do an assign such as :
assign b_int[0] = b_0_int ;
.
.
.
.
.
assign b_int[127] = b_127_int;
This adds about 128 buffers just for the usage of the modulexyz 128 times. In the above example, I have the b_int mentioned as 8 bits, but how about when the width of it increases. I want to have variability on fly. This is how i meant more code (as a result more buffers).

Thankyou for the alternatives suggested!
Although , Option 1) is not feasible when the variable used is of higher width. and Option 2) woudn’t be right as i want “b” of modulexyz to receive just b_0_int and not the concatenated value.

Hence I see the need to use define macros. Is the usage of define not possible ?

4

In reply to randomcoder:

You still did not explain why you need individually named signals instead of using an array in the first place.

As you are already aware, `define macros get expanded before any parsing any SystemVerilog code. There is no way to have a macro loop. Your only other option is using an external macro processor. That can make debugging much more difficult.

5

In reply to dave_59:

Well, i have my signal named as b_*_int . That is why i want to have individually named signals. The only solution i see is FORM AN ARRAY from those individual signals like :

reg [127:0] b_int [127:0] ;
assign b_int[0] = b_0_int ;
.
.
.
.
.
assign b_int[127] = b_127_int;

and then use it in my module as :

generate
for (genvar i=0; i<128; i++) begin
modulexyz xyz ( .a(a),
.b(b_int[i])
);

Do you see a more cleaner way of this usage, without the assign statements ?