Topics tagged define-macro

Topic	Replies	Views	Activity
String concatenation inside generate block SystemVerilog SystemVerilog , generate-macro-define , define-macro , generate-block , Assignment-inside-generate-block , string-concatenation	4	6513	December 14, 2017
How to mimic static constructor in SystemVerilog? SystemVerilog SystemVerilog , new-function , define-macro , static-method , static-constructor	2	1628	May 20, 2016
Real numbers for `define macro SystemVerilog SystemVerilog , define-macro , real-numbers	1	1691	July 15, 2014