Real numbers for `define macro

SystemVerilog
, ,
1

I’m planning to use a real number for `define macro.


`define LTOL 0.8
`define HTOL 1.2

But when I tried to use display, the result is:


$display("LTOL = %0.2f, HTOL = %0.2f", `LTOL, `HTOL);

// Result
LTOL = 2.00, HTOL = 2.00

It seems that using real numbers in `define macro is not working.
Is there a way to make this work?
And why does the result print a value of 2.00?

Thanks.

2

Oh my bad… The reason why I’m getting other values for LTOL and HTOL is because I have other declaration of it in other file.

This is now okay. Real numbers can be used in `define macro.