Assertion macros

SystemVerilog
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1

I’m writing assertion macros and want to pass hierarchical name eg out.vld. But I’m getting an error of illegal location for a hierarchical name while passing it as an argument to the macro `assert_xyz_p(out.vld, in.sel,in.col), Is there a way I can pass hierarchical arguments?

2

In reply to Nimisha Varadkar:

Macros have no knowledge of SystemVerilog syntax—they just do simple text replacement. You need to make sure to text replaced by the macro is valid syntax.

3

In reply to dave_59:

Thanks, Dave!