Define macro to substitute reg name in regmodel

SystemVerilog
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1

Hi,

I want to use register name in the regmodel hierarchy depends on some define.

  1. When SINGLE_COUNTER is defined as `define SINGLE_COUNTER:
    if(m_regmodel_inst.REG1.FIELD.get_mirrored_value()) begin …

  2. when SINGLE_COUNTER is not defined:
    if(m_regmodel_inst.REG1[cntr_no].FIELD.get_mirrored_value()) begin …

Similar way, want to use different registers also.

Can I create macro using define to get the reg name (either "with index" or "without index") ? So that would be easy to replace as below: if(m_regmodel_inst.REG_NAME(REG1, idx).FIELD.get_mirrored_value()) begin

If its possible, how to define `REG_NAME(REG1, idx) ?

Thanks in advance.

2

In reply to kansagaratushar:


//without index
`define REG_NAME(REG,IDX) ``REG

//with index
`define REG_NAME(REG,IDX) ``REG[``IDX]