SystemVerilog include import


This is content of my tb.f file.


Thing is that there are two classes in each package that uses each other.
I tried to import each package to another and i get recursive import error, obviously.
Then i tried to typedeff one class to tell compiler that it will be defined later but in that case it says that
Forward declaration for type ‘command_transaction’ was not defined.. I think it is because these to packages are not in the same scope (because thats how questa works, but i am not sure). How should i overcome this problem.
One more thing. What does creating work library does to my project? I thought i can see all the files that i compiled before in any of the next compiled files, but i am wrong.
Also, i used scripts that wrote someone else and everything that i mentioned above worked perfectly. How to overcome this scope problem in scripts beside importing files one to another?
Any direction where to look is wellcomed.

In reply to Sanjin_Arsenovic:

Your register model should be DUT specific and independent of any agent type. There should be no reason to use anything from your agent package in the register model. Also, your agent package should be independent from the register model, so I don’t understand why you have circular references.

Can you show more information so we can provide better advice on how to architect your environment?

In reply to cgales:

My register_adapter was in reg_pkg and it used command_transaction whitch is part of the agent. I simply moved register_adapter to agent and solved collision problem, but i still want to know how to solve situtaion that i described in general.
If i have two packages:
package P;
class A;
int i;
B b1;
endclass : A
endpackage : P

package Q;
class B;
int j;
A a1;
endclass : B
endpackage : Q

How to put them in the same scope in questa?
When i try to typedeff one class it says that
Forward declaration for type ‘command_transaction’ was not defined.

In reply to Sanjin_Arsenovic:

You should never have this situation as it creates a infinite loop of references. You will end up with A → b1 → a1 → b1 → a1 → … ad infinitum.

However, if you were to implement this, it would have to be within a single package. SystemVerilog requires all classes to be fully defined within a package, either by implementation or import. A typedef does not meet this requirement.

In reply to cgales:

thank you